HP B160L Bedienungsanleitung Seite 75

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PA-RISC Buses Runway
Attach to Runway with 64-bit
Two I/O adapters (IOAs) per U2/UTurn chip
Maximum data rate depends on Runway clock with 120MHz and 64-bit: 960MB/s
4. GSC+, the main system bus, attach to the U2/UTurn IOAs
Attaches via 32-bit at a fraction of Runway/IOA clock, mostly 40MHz
PA-7300LC systems use the extended GSC version
5. I/O adapters and slots attach to GSC+
LASI chipset
Video adapters
I/O slots extend GSC
Bus adapters, including EISA, VME and PCI, attach to GSC+
Runway+/Runway DDR CPU attachments
The PA-8500, PA-8600, PA-8700 processors use an advanced version of the Runway system bus with
increased data rate and utilized different I/O and memory controllers, with most using the Astro chipset
(IOMMU) and few servers the sophisticated Stretch and Cell chipsets.
Described below is the common configuration with Astro chipset for the Stretch/Cell bus attachments
see their entries at the Chipset page.
1. Runway+/Runway DDR is the main processor and memory bus
1-4 CPUs attach to Runway with 64-bit, parity-protected
SMP-capable
2. Astro is the main memory and I/O controller which attaches to Runway
Attaches to Runway+/Runway DDR with 64-bit at maximum of 125MHz (with in this case
2.0GB/s peak data rate)
Memory attaches to Astro with a peak data rate of about 2.0GB/s at 125MHz
Up to eight I/O links (ropes) with each 250MB/s attach to Astro
3. Elroy I/O adapters attach PCI bridges via the I/O ropes to Astro
One or two ropes per Elroy PCI bridge
PCI slots or devices attach to Elroy bridges
4. PCI, the main I/O buses, attach to the multiple Elroy bridges
33 or 66MHz, 32 or 64-bit
5. I/O devices, adapters and slots attach to PCI
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