
PA-RISC CPU Architecture Transition Lookaside Buffer (TLB)
PA-7200 - 120 combined entries
PA-7300LC - 96 combined entries
PA-8000 - 96 combined entries
PA-8200 (PCX-U+) - 120 combined entries
PA-8500 (PCX-W) - 160 combined entries
PA-8600 (PCX-W+) - 160 combined entries
PA-8700 (PCX-W2) - 240 combined entries
PA-8800 - 2×240 combined entries
PA-8900 - 2×240 combined entries
Hitachi’s PA-RISC 1.1 derivates also used split TLBs:
Hitachi PA/50 - 32 I and 64 D entries
Hitachi HARP-1 - 128 I and 128 D entries (some sources mention a second-level TLB)
Most interestingly, the older PA-RISC 1.0 processors (pre-PA-7000) have huge TLBs (even for today’s
standards):
TS-1 - 4096 entries (split I/D)
NS-1 - 4096 entries (split I/D)
NS-2 - 16384 entries (split I/D)
CMOS26B (PCX) - 8192 entries (split I/D)
The TLB memory on these earlier CPUs was implemented mostly off-chip/off-die via separate memory
(SRAM) chips.
Translation process
PA 1.1: If a virtual address has to be translated to a physical address, the corresponding TLB is
searched for an entry matching the Virtual Page number. If an entry is found, the 20-bit Physical
Page number, delivered by the TLB, is concatenated with the original 12-bit page offset to the
build up the 32-bit absolute physical address.
TLB miss handling implementations
Hardware: If the CPU implementation provides a hardware TLB miss handler, it attempts to find
the virtual-to-physical translation in the Page Table. If successful, the translation and protection
fields are inserted in the TLB. If not successful, an interruption occurs so the software miss handler
can complete the translation.
Software: If software TLB miss handling is implemented, a TLB miss fault interruption routine
performs the translation. It inserts the translation and protection fields in the TLB and afterward
restarts the interrupted routine, in which the TLB miss occurred.
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