HP B160L Bedienungsanleitung Seite 21

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PA-RISC Processors PA-7100LC (PCX-L) (Hummingbird)
References
1. Various
2. A 200 MFLOP HP PA-RISC Processor
10
(.pdf) W. Jaffe, B. Miller, J. Yetter (1992: Hewlett
Packard. Proceedings of IEEE Hot Chips IV)
3. Multiprocessor Features in a PA-RISC Processor Interface Chip
11
(.pdf) T. Alexander et al (1992:
Hewlett Packard. Proceedings of IEEE Hot Chips IV)
4. Évolution des gammes de processeurs MIPS, DEC Alpha, PowerPC, SPARC, x86 et PA-RISC
12
(PDF) André Seznec and Thierry Lafage (INRIA: June 1997)
2.2.6 PA-7100LC (PCX-L) (Hummingbird)
Used in
712, 715, 725
743i, 748i
D200, D210, D300, D310
E25, E35, E45, E55
Hitachi 3050RX 225, 235, 255, 535, e9000V V715, V715Tiny, VE25, VE35, VE45, VE55
SAIC Galaxy 1100
Time of introduction
1994
Overview
The PA-7100LC was primarily designed as a single-chip solution for application in low cost systems
while still delivering the performance of 1991 high-end workstations and servers. The CPU core design
was leveraged from the PA-7100 and integrated with several of its off-chip support components on a
single die. The PA-7100LC integrates the CPU, FPU, MIOC (memory and I/O controller) and a first-
level cache on a single VLSI chip and has a direct attachment to the GSC main bus. Both CPU and FPU
support the PA-RISC 1.1 Edition 3 ISA.
Details
PA-RISC version 1.1c 32-bit
Three functional units: 2 integer ALUs, 1 Floating Point unit (See Note 1)
2-way superscalar
10
http://www.hotchips.org/archives/hc4/2_Mon/HC4.S1/HC4.1.2.pdf
11
http://www.hotchips.org/archives/hc4/2_Mon/HC4.S2/HC4.2.1.pdf
12
ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-3188.pdf
14
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