HP B160L Bedienungsanleitung Seite 30

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PA-RISC Processors PA-8500 (PCX-W) (Vulcan)
Runway system/memory bus, 120MHz, 64-bit wide, featuring split transactions and glueless
multiprocessing. Max. throughput of 960MB/s
CPU interfaces to UTurn I/O adapters and MMC/SMC memory controllers on the Runway bus
Up to 300MHz frequency with 3.3V core voltage
17.7×19.6 mm
2
die, 4,500,000 FETs, 0.5µ(micron), 5-layer metal CMOS packaged in a 1,085-
pin flip-chip LGA package
References
Four-Way Superscalar PA-RISC Processors
24
(PDF, 190KB) Anne P. Scott et al (August 1997:
Hewlett-Packard Journal).
HP Pumps Up PA-8x00 Family
25
(archive.org mirror) Linley Gwennap (October 1994: Micro-
processor Report, Volume 10 Number 14). [Article reprint for vanished cpu.hp.com]
2.2.11 PA-8500 (PCX-W) (Vulcan)
Used in
A400-44 (rp2400), A500-44 (rp2450)
B1000, B2000
C360, C3000
J5000, J7000
L1000-36, L1000-44 (rp5400), L2000-36, L2000-44 (rp5450)
N4000-36, N4000-44 (rp7400)
V2500
Stratus Continuum 419, 429, 616S, 616, 619, 629, 1219, 1229
Time of introduction
September 1998
Overview
The PA-8500 processor is a direct evolution of the PA-8000 and PA-8200 processors, taking over a
very similar processing core. However, the PA-8500 implemented large on-die L1 caches, a first for
PA-RISC processors and a break with the long-standing HP tradition of keeping the large L1 caches
off-chip. (The two years older PA-7300LC also includes on-chip L1 caches, albeit much smaller). There
were no other significant changes to the processing core, besides small increases to the TLB and BHT.
24
http://ftp.parisc-linux.org/docs/whitepapers/four_way_superscalar.pdf
25
http://web.archive.org/web/20040214112604/http://www.cpus.hp.com/technical_references/101996ar.shtml
23
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