
PA-RISC Processors PA-8200 (PCX-U+) (Vulcan)
Off-chip L1 caches up to 1MB I and 1MB D, realized in synchronous 6.7ns (150MHz) late-write
1Mb SRAMs, one cycle latency
Caches are direct-mapped and dual-ported
56-entry instruction queue/reorder buffer (IRB)
MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG
decoding
Each instruction includes five predecode bits
Bi-endian support
Runway system/memory bus, 120MHz, 64-bit wide, featuring split transactions and glueless
multiprocessing. Max. throughput of 960MB/s
CPU interfaces to UTurn I/O adapters and MMC/SMC memory controllers on the Runway bus
Up to 180MHz frequency with 3.3V core voltage
17.7×19.6 mm
2
die, 4,500,000 FETs, 0.5µ(micron), 5-layer metal CMOS packaged in a 1,085-
pin flip-chip LGA package
References
Advanced Performance features of the 64-bit PA-8000
21
(archive.org mirror) Doug Hunt (1995:
IEEE CS Press CompCon 5). [Article reprint for cpus.hp.com]
PA-8000 Combines Complexity and Speed
22
(archive.org mirror) Linley Gwennap (1994: Micro-
processor Report, Volume 8 Number 15). [Article reprint for vanished cpus.hp.com]
Four-Way Superscalar PA-RISC Processors
23
(PDF, 190KB) Anne P. Scott et al (August 1997:
Hewlett-Packard Journal).
2.2.10 PA-8200 (PCX-U+) (Vulcan)
Used in
C200, C240
D390
J2240
K370, K380, K570, K580
R390
V2200, V2250
21
http://web.archive.org/web/20040214092531/http://www.cpus.hp.com/technical_references/advperf.shtml
22
http://web.archive.org/web/20040214122429/http://www.cpus.hp.com/technical_references/111994ar.shtml
23
http://ftp.parisc-linux.org/docs/whitepapers/four_way_superscalar.pdf
21
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