HP B160L Bedienungsanleitung Seite 15

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PA-RISC Processors Early PA-RISC
4. TLB, the translation lookaside buffer with 4096 entries for 2KB pages
5. Cache controller with split instruction and data caches 64KB for each I and D
6. FPC, the floating-point coprocessor, handles FP operations parallel to the CPU/ALU (the
ADD/MUL/DIV chip was taken over from the HP 9000/550 FOCUS system)
4096-entry TLB off-chip, direct-mapped
Off-chip L1 cache of 128KB (I/D) direct-mapped/one-way associative
Physical address space of 27-bit (128MB main memory could be addressed)
8MHz clock speed
Six (some sources say five) printed circuit boards, implemented in FAST TTL and (25ns and 35ns)
SRAMs/PALs, which each about 150 ICs
NS-1
Used in: 825, 835, 850
Introduced in: 1987
The first implementation of PA-RISC in a NMOS fabrication process followed shortly on the original
TTL-based TS-1 and was called NS-1. The NS-1 processor is integrated on one circuit board (two on
825 server) with the CPU as single NMOS-III chip supplemented by external support chips:
Details:
PA-RISC version 1.0 32-bit
Three-stage pipeline
CPU is a single chip, with eight support VLSI chips
1. SIU (system interface unit), attaches the CPU to the SMB main bus
2. two CCUs (cache controller units CCU0 and CCU1), attach to separate external cache chips
3. TCU (TLB controller unit), attaches to the external TLB chips
4. MIU (math interface unit), controls three third-party floating point (FP) chips (ADD, MUL
and DIV)
2048 to 4096-entry TLB off-chip
Off-chip L1 cache of 16KB (HP 9000/825) to 128KB (others), unified
Physical address space of 29-bit (512MB main memory could be addressed)
CPU attaches via System Main Bus (SMB) to memory and I/O (controllers)
SMB is a synchronous, pipelined bus with 64-bit wide address and data transfers
25-30MHz clock speed
One circuit board (two boards on HP 9000/825), 144,000 FETs, implemented in NMOS-III
packaged in a 272-pin ceramic PGA package
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