
PA-RISC Processors PA-7000 (PCX-S) (Cheetah)
2.2.4 PA-7000 (PCX-S) (Cheetah)
Used in
705, 710, 720, 730, 750
F10, F20, F30, G30, G40, H20, H30, H40, I30, I40
Mitsubishi ME/R7200, ME/S7200, ME/R7300, ME/S7300, ME/R7500, ME/S7500
Time of introduction
1991
Overview
The PA-7000 was the first PA-RISC version 1.1 processor and first used in the new 700 series worksta-
tions and later in some of the Nova servers. The PA-7000 is a multi-chip implementation:
Central CPU with ALU, TLB and the I/D cache controllers
Viper Memory and I/O Controller (MIOC)
External FPU
PBus/VSC interface, buffer chips for data/addresses between VSC and PBus
Details
PA-RISC version 1.1a 32-bit
Needs external FPU (commonly used was a coprocessor developed by HP and Texas Instruments)
Five-stage pipeline
96/96 I/D TLB
4/4 I/D BTLB
32-bit bus to I cache
64-bit bus to D cache
PBus 32-bit from processor to the Memory and I/O Controller (MIOC)
Off-chip caches up to 256KB/256KB I/D
Up to 66MHz frequency with 5.0V core voltage
14.2×14.2 mm
2
die, 577,000 FETs, 1.0µ(micron), 2-layer CMOS (CMOS26B) in 408-pin CPGA
External FPU fabbed in 13.0×13.0 mm
2
die, 640,000 FETs, 0.8µ(micron), TI EPIC-2 in 207-pin
CPGA
11
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