
PA-RISC Processors PA-7100/PA-7150 (PCX-T) (Thunderbird)
The PA-7150 is a PA-7100 with tweaks to the core and cache subsystem to allow clock frequencies up
to 125MHz.
The PA-7100 was hardware developed on an HP 9000/I-Class server.
Details
PA-RISC version 1.1b 32-bit
Two functional units: 1 integer ALU, 1 Floating Point unit
2-way superscalar
SMP-capable
CPU, FPU, MMU and cache controller on one chip, memory and I/O controller (Viper MIOC)
off-chip
Five-stage pipeline
Pipeline store technique for reduction of penalty for execution of any store to data cache
Stall-on-use mechanism for parallel procession of instruction streams and cache misses
3-instruction queue
Hardware TLB miss handler
Hardware static branch support
I/D cache bypass (7150)
Off-chip L1 caches up to 1MB I and 2MB D realized in asynchronous standard SRAMs
I/D caches are both 64-bit per access, direct mapped, parity protected and cycled at CPU clock
Caches are attached directly to the CPU
Caches are software accessible
Caches are virtually indexed and physically tagged to minimize latency
120-entry fully associative TLB
16-entry BTLB with programmable page sizes up to 64MB
CPU attaches via PBus to the Viper memory and I/O controller (MIOC)
PBus is 32-bit multiplexed address/data bus and probably runs at possible bus speeds of 1.0, .67
and .50 of processor speed
Two different multiprocessing connection strategies supported (shared MIOC or dedicated MIOCs)
MP cache coherency support
Up to 100MHz frequency (PA-7100) with 5.0V core voltage
Up to 125MHz frequency (PA-7150) with 5.0V core voltage
14.0×14.0 mm
2
die, 850,000 FETs, 0.8µ(micron), 3-layer metal CMOS (CMOS26B process)
packaged in a 504-pin ceramic PGA package
Power dissipation of 30W at 100MHz
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