
PA-RISC Processors PA-8800 (Mako)
Details
PA-RISC version 2.0 64-bit
Twenty functional units: four integer ALUs, four shift/merge units, four complete load/store
pipelines, four Floating Point multiply/accumulate units, four Floating Point divide/square root
units
4-way superscalar
Two address adders
SMP-capable
External memory and I/O controllers
240-entry fully-associative dual-ported TLB per core
32-entry BTAC (branch target address cache) per core
2048-entry BHT (branch history table) per core
Dynamic and static branch prediction modes
0.75MB I and 0.75MB D on-chip L1 caches per core
No data passing between the cores’ L1 caches
32MB off-chip L2 cache, four-way associative, physically indexed and tagged
L2 cache is shared between both CPU cores
L2 cache controller is on-die
L2 implemented in DDR-ESRAM, four 8MB chips, 300MHz clock, each 2.7GB/s bandwidth
Total >10GB/s L2 cache bandwidth
1MB SRAM tags for L2 cache
ECC for L2 data and tags
MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g., MPEG
decoding
Itanium 2/McKinley processor bus, 200MHz clock ( “double-pumped” ), 128-bit datapath, 6.4GB/s
bandwidth, data ECC-protected, signals parity
CPU interfaces to the Cell chipset or the zx1 chipset’s MIO
Up to 1 GHz frequency with 1.5V core voltage
23.6×15.5 mm
2
die, 300,000,000 FETs, 0.13µ(micron), 8-layer Silicon-on-Insulator CMOS (fabbed
by IBM)
References
HP’s Mako Processor
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(PDF, 1.4MB) David J. C. Johnson (2001: Microprocessor Forum).
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http://ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf
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