HP B160L Bedienungsanleitung Seite 279

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HP 9000 rp3410 & rp3440 Internals
1. Processor bus (6.4GB/s) for one (rp3410) or two (rp3440) CPUs
2. Two independent memory buses (each 4.25GB/s)
3. The I/O channels (via the IOAs, see below) six on rp3410 (3.0GB/s) and eight on rp3440
(4.0GB/s)
The zx1 MIO also contains both memory and cache controllers.
The rp3410 and rp3440 have different I/O configurations based on IOAs:
rp3410: Five zx1 IOAs (I/O adapters) connect the PCI-X slots and I/O devices to the zx1 MIO
with an aggregate bandwidth of 3.0GB/s on six 0.5GB/s channels
1. PCI-X 64/133 I/O slot on two channels 1.0GB/s
2. PCI-X 64/133 I/O slot on one channel 0.5GB/s
3. Management LAN and serial ports (iLO card) on one channel 0.5GB/s
4. Ultra160 SCSI and Gigabit Ethernet controllers on one channel 0.5GB/s
5. IDE and USB controllers one channel 0.5GB/s
rp3440: Seven zx1 IOAs (I/O adapters) connect the PCI-X slots and I/O devices to the zx1 MIO
with an aggregate bandwidth of 4.0GB/s on eight 0.5GB/s channels
1. PCI-X 64/133 I/O slot on two channels 1.0GB/s
2. PCI-X 64/133 I/O slot on one channel 0.5GB/s
3. PCI-X 64/133 I/O slot on one channel 0.5GB/s
4. PCI-X 64/133 I/O slot on one channel 0.5GB/s
5. Management LAN and serial ports (iLO card) on one channel 0.5GB/s
6. Ultra160 SCSI and Gigabit Ethernet controllers on one channel 0.5GB/s
7. IDE and USB controllers on one channel 0.5GB/s
The “I/O connectivity” part of the chipset is made up of standard third-party I/O chips:
Dual-channel Ultra160 SCSI controller (LSI Logic 53C1030)
Gigabit Ethernet controller (Broadcom Tigon 3)
IDE controller (PCI649)
USB2.0 controller
Buses
Itanium 2/zx1 processor bus, 128-bit, 200MHz, 6.4GB/s
Two independent zx1 memory buses, 266MHz, each 4.25GB/s aggregate 8.5GB/s memory
bandwidth
rp3410:
Six zx1 I/O channels/buses, aggregate 3.0GB/s
Two PCI-X 64/133 I/O buses
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