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PA-RISC Processors PA-8000 (PCX-U) (Onyx)

 Stratus Continuum 628, 1228

Time of introduction

January 1996

Overview

The PA-8000 is a four-way superscalar 64-bit processor with aggressive out-of-order (OoO) execution

capabilities. It has four integer, four ﬂoating-point and dual load/store units, a large OoO dispatch win-

dow and, following a long HP tradition, no on-chip caches. The PA-8000 is the ﬁrst chip to implement

the 64-bit PA-RISC 2.0 architecture which includes many extensions to support 64-bit computing. This

includes that all integer registers and functional units (ALU, shift/merge) have been widened to 64-bit

to support native 64-bit integer computing. The ﬂat address space was also extended from 32- to 64-bit

— however, PA-RISC 2.0 processors support only a physical address space/addressable physical mem-

ory of 40-bit/1TB (PA-8000 to PA-8600) to 44-bit/16TB (PA-8700 and up). Other extensions in the

PA-8000 include fast TLB insert instructions, memory prefetch instructions, support for variable sized

pages, branch prediction hinting and new FPMAC (Floating Point Multiply Accumulate) units. The

instruction decode logic is not integrated with the functional units’ pipeline logic, which allows the

chip to partially decode instructions in advance of the actual execution (by the functional units).

A key feature of the PA-8000 and all other PA-RISC 2.0 processors is the IRB (Instruction Reorder

Buffer), which enables the processor to perform its own instruction scheduling in hardware, indepen-

dent of compiler or other software technologies. The IRB can store up to 28 computation and 28

load/store instructions; it tracks interdepencies between these instructions and allows execution as soon

as they are ready. Also tracked are branch prediction outcomes and with re-scheduling the CPU can

execute instructions past cache misses. The IRB plays the key part in the OoO execution capabilty of

the chip.

Details

 PA-RISC version 2.0 64-bit

 Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2

Floating Point multiply/accumulate units, 2 Floating Point divide/square root units

 4-way superscalar

 SMP-capable

 External memory and I/O controllers

 Two address adders

 96-entry fully-associative dual-ported TLB

 TLB miss penalty of 61 cycles

 32-entry BTAC (Branch Target Address Cache)

 256-entry BHT (Branch History Table)

 Dynamic and static branch prediction modes

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HP B160L Bedienungsanleitung Seite 27