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7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 183

UG471 (v1.5) May 15, 2015

Figure A-1 illustrates each of these terminations.

TMDS_33 Far 3.3V 50Ω

Notes:

1. All differential versions of the HSTL, SSTL, HSUL, and MOBILE_DDR standards (e.g., DIFF_SSTL135)

have the same termination as the single-ended versions.

Table A -1: Default Terminations for SSN Noise Analysis by I/O Standard (Cont’d)

IO Standard

(1)

Default Termination

1 2 ... 178 179 180 181 182 183 184 185 186

7 Series FPGAs 1
SelectIO Resources 1
Revision History 2
Table of Contents 5
UG471 (v1.5) May 15, 2015 10
About This Guide 11
Preface: About This Guide 12
New Features 14
7 Series FPGA I/O Bank Rules 17
Introduction 19
Xilinx DCI 20
DCIRESET Primitive 22
DCI Cascading 22
DCI and 3-state DCI (T_DCI) 28
DCI Usage Examples 31
IBUF and IBUFG 35
IBUF_IBUFDISABLE 35
IBUF_INTERMDISABLE 36
IBUFDS and IBUFGDS 36
IBUFDS_DIFF_OUT_IBUFDISABLE 37
IBUFDS_IBUFDISABLE 37
IBUFDS_INTERMDISABLE 38
IBUFDS_DIFF_OUT_INTERMDISABLE 38
IOBUF_DCIEN 39
IOBUF_INTERMDISABLE 40
IOBUFDS_DCIEN 41
IOBUFDS_DIFF_OUT 42
IOBUFDS_DIFF_OUT_DCIEN 43
IOBUFDS_INTERMDISABLE 44
DCI_CASCADE Constraint 46
Location Constraints 47
IOSTANDARD Attribute 47
IBUF_LOW_PWR Attribute 47
Output Slew Rate Attributes 48
VCCAUX_IO Constraint 50
LVTTL (Low Voltage TTL) 51
LVCMOS (Low Voltage CMOS) 54
LVDCI _ DV2 57
HSLVDCI (High-Speed LVDCI) 59
HSTL_ I and HSTL_ I_18 60
HSTL_I_12 60
HSTL_ II and HSTL_ II_18 60
N/A Available 62
External Termination 63
Differential HSTL Class I 64
HSTL Class II 66
Differential HSTL Class II 68
Not 3-stated 72
(T pin logic Low) 72
3-stated 72
(T pin logic High) 72
SSTL18_I, DIFF_SSTL18_I 76
DIFF_SSTL135 76
User Guide for details 77
HSUL_12 and DIFF_HSUL_12 84
Example Board Topology 85
Differential HSUL_12 86
MOBILE_DDR (Low Power DDR) 88
Transmitter Termination 91
Receiver Termination 91
Differential Clock 93
Input to the FPGA 93
BLVDS (Bus LVDS) 96
Table 1-55: V 99
Chapter 1: SelectIO Resources 102
SelectIO Logic Resources 105
ILOGIC Resources 106
ZHOLD_DELAY 108
OPPOSITE_EDGE Mode 109
SAME_EDGE Mode 110
SAME_EDGE_PIPELINED Mode 110
Input DDR Resources (IDDR) 111
ILOGIC Timing Models 112
Clock Event 4 113
Clock Event 1 113
Clock Event 9 114
IDELAYE2 Primitive 115
IDELAY Ports 116
IDELAYRESOLUTION 117
IDELAY Attributes 118
IDELAY Modes 119
IDELAY Timing 120
Clock Event 2 121
Clock Event 3 121
Clock Event 0 122
IDELAYCTRL 123
IDELAYCTRL Timing 124
IDELAYCTRL Locations 124
OLOGIC Resources 125
Output DDR Overview (ODDR) 126
Clock Forwarding 127
Output DDR Primitive (ODDR) 128
OLOGIC Timing Models 128
Timing Characteristics 129
ODELAYE2 Primitive 133
ODELAY Ports 134
ODELAY Attributes 136
ODELAY Modes 137
ODELAY Timing 138
Chapter 3 141
ISERDESE2 143
Primitive 143
Registered Outputs – Q1 to Q8 144
Combinatorial Output – O 145
Bitslip Operation - BITSLIP 145
High-Speed Clock Input - CLK 146
High-Speed Clock Input - CLKB 146
Divided Clock Input - CLKDIV 146
Oversampling Mode - OCLK 147
Reset Input - RST 147
ISERDESE2 Attributes 148
DATA_RATE Attribute 149
DATA_WIDTH Attribute 149
INTERFACE_TYPE Attribute 149
ISERDESE2 Clocking Methods 150
MEMORY Interface Type 151
MEMORY_QDR Interface Type 151
OVERSAMPLE Interface Type 151
ISERDESE2 Width Expansion 153
OSERDESE2 154
BITSLIP Submodule 156
After Clock Event 3 158
OSERDESE2 Primitive 160
Data Path Output - OQ 161
DATA_RATE_OQ Attribute 163
DATA_RATE_TQ Attribute 163
SERDES_MODE Attribute 164
TRISTATE_WIDTH Attribute 164
OSERDESE2 Width Expansion 165
Output Feedback 166
OSERDESE2 Latencies 166
IO_FIFO Overview 171
FIFO Core 172
7 Entries Deep 172
Register Register 172
IN_FIFO Primitive 173
Table 3-15: IN_FIFO Ports 174
OUT_FIFO 175
OUT_FIFO Primitive 176
Table 3-18: OUT_FIFO Ports 177
Resetting the IO_FIFO 178
EMPTY and FULL Flags 178
Termination Options for 181
SSO Noise Analysis 181
TMDS_33 Far 3.3V 50Ω 183
IO Standard 183
Default Termination 183

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