HP Integrity rx2600 Spezifikationen PDF herunterladen (Seite 21)

I/O channels link to three PCI buses, which in turn link to the core LAN, SCSI, IDE, and USB interfaces and to the

management processor.

Architectural overview of the HP Integrity rx2600 server

The HP Integrity rx2600 server supports either one or two Intel Itanium 2 processors linked to the HP zx1 Chipset

memory and I/O controller through a 200 MHz, double-pumped 128-bit front-side system bus. Total bandwidth

on the system bus is 6.4 GB/s.

Figure 11. The HP Integrity rx2600 server architecture features Intel Itanium 2 processors and the HP zx1 Chipset

Memory DIMMs are attached directly to two 266 MHz, 4.3 GB/s memory buses. Combined memory bandwidth

across both buses is 8.5 GB/s. Each bus links up to six DDR DRAM memory DIMMs. Total system memory

capacity is 24 GB, via twelve 2 GB DIMMs.

The I/O architecture consists of eight 0.5 GB/s channels allocated among seven zx1 Chipset I/O adapters. Each

of these seven adapters provides a PCI-X or PCI bus to the available I/O slots and core I/O devices. The first two

channels connect to a single 133 MHz PCI-X I/O slot, providing 1 GB/s of sustained throughput. This slot is ideal

for high-bandwidth I/O adapters such as high-performance clustering interconnect. The next three I/O channels

link to three independent 133 MHz PCI-X I/O slots, each with 0.5 GB/s of sustained throughput. The remaining

three I/O channels link to three PCI buses, which in turn link to the core LAN, SCSI, IDE, and USB interfaces and

to the management processor.

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 29 30

Keine Kommentare

HP Integrity rx2600 Spezifikationen Seite 21