HP Server tc2100 Informationsblatt

Memory technology evolution: an overview of system memory technologies technology brief, 8th edition Abstract...

Memory channel interleaving Multi-core processors running multi-threaded applications pose a significant challenge to the memory subsystem. The proces

Advanced memory technologies Despite the performance improvement in the overall system due to use of SDRAM, the growing performance gap between the me

Double transition clocking Standard DRAM transfers one data bit to the bus on the rising edge of the bus clock signal, while DDR-1 uses both the risin

DDR-1 DIMMs DDR-1 DIMMs require 184 pins instead of the 168 pins used by standard SDRAM DIMMs. DDR-1 is versatile enough to be used in desktop PCs or

DDR-3 DDR-3, the third-generation of DDR SDRAM technology, will make further improvements in bandwidth and power consumption. Manufacturers of DDR-3 w

Fully-Buffered DIMMs Traditional DIMM architectures use a stub-bus topology with parallel branches (stubs) that connect to a shared memory bus (Figure

Consequently, JEDEC developed the Fully-Buffered DIMM (FB-DIMM) specification, a serial interface that eliminates the parallel stub-bus topology and a

Challenges The challenges for the FB-DIMM architecture include latency and power use (thermal load). Memory latency is the delay from the time the dat

Rambus DRAM Rambus DRAM (RDRAM) allows data transfer through a bus operating in a higher frequency range than DDR SDRAM. In essence, Rambus moves smal

19 With the high data rate of Rambus, signal integrity is troublesome. System boards must be designed to accommodate the extremely stringent timing of

Abstract The widening performance gap between processors and memory along with the growth of memory-intensive business applications are driving the ne

For more information For additional information, refer to the resources listed below. Resource description Web address JEDEC Web site http://www.je

Each DRAM chip contains millions of memory locations, or cells, which are arranged in a matrix of rows and columns (Figure 1). On the periphery of the

are many mechanisms to refresh DRAM, including RAS only refresh, CAS before RAS (CBR) refresh, and Hidden refresh. CBR, which involves driving CAS act

Figure 3. Representation of a bus clock signal Over the years, some computer components have gained in speed more than others have. For this reason

additional data sections are accessed with every clock cycle after the first access (6-1-1-1) before the memory controller has to send another CAS. F

Bank interleaving SDRAM divides memory into two to four banks for simultaneous access to more data. This division and simultaneous access is known as

DIMM Configurations Single-sided and double-sided DIMMs Each DRAM chip on a DIMM provides either 4 bits or 8 bits of a 64-bit data word. Chips that pr

Parity and ECC DIMMs The ninth DRAM chip on one side of a DIMM is used to store parity or ECC bits. With parity, the memory controller is capable of d